Q: It is unclear whether the SAI blocks are Slave only or do they support Master mode too?

A: The SAI blocks work in Slave mode only

Q: We expect to configure the SAI in Synchronous mode and each of the peripheral shown has 5 critical signals (Bit Clk, Fsync, Din Dout & Mclk). The SAI blocks however has 7 signals (TX Bit Clk, RX Bit Clk , TX Fsync, RX Fsync, TX Data, RX Data & Mclk). How does the mapping work in this case?

A: SAI Block has 6 signals (TX Bit Clk, RX Bit Clk , TX Fsync, RX Fsync, TX Data, RX Data) and TX signals are multiplexed with Rx signals. Hence only one can be used at a time.This requires that 2 SAI modules are used per CODEC.

Q: For instance TX Data & RX Data are mapped to the same physical pin on the SOC, (SAI4 TX_DATA and RX_DATA mapped to EC1_TXD2) how do I map 2 external signals to a single pin on SOC?

A: Using RCW

Q: In our environment, we need solutions that are available over a very long period of time (up to 15 years). How long are your modules available?

A: Using NXP CPUs on our SoMs we are able to provide an availability of 15 years from the time of the launch of the CPU. With LTB and long-time stocking we are even able to extend this period.

RCW[EC1_SAI4_5_PMUX] = 0b010 - { SAI5_TX_DATA, SAI4_TX_DATA, SAI5_TX_SYNC, SAI4_TX_SYNC, SAI5_TX_BCLK, SAI4_TX_BCLK}

RCW[EC1_SAI4_5_PMUX] = 0b011 – {SAI5_RX_DATA, SAI4_RX_DATA, SAI5_RX_SYNC, SAI4_RX_SYNC,SAI5_RX_BCLK, SAI4_RX_BCLK}