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| 30/01/2007 | For the MPX8349FA Module (processor module with MPC8349 and Altera FPGA), MicroSys offers a companion chip solution implemented by Wiese Signalverarbeitung GmbH. It is an IP-Core, which allows the usage of the various and standardized Avalon components of the ALTERA FPGA family. This IP-Core offers the possibility to map the Local Bus Interface of the MPC8349 as a master per chip select to the Avalon bus. With an integrated Interrupt Master all other interrupt capable Avalon components can be vectorized and mapped to specific interrupt inputs of the processor. Of course, as with all other Avalon Masters, a file (system.h) is created, which contains a complete map of all the addresses and interrupts of the used Avalon components. Another way to use the IP-Core, which is available in parallel, allows the direct implementation of slave components within the FPGA and outside of the Avalon interface. The bus mapping is done without the need to write a single line of VHDL code. Both usage models are available per chip select and are configured in the SOPC builder. The IP-Core is available as so called Opencore Plus variant and allows a complete and free of charge design evaluation for the end customer The installation package for the IP-Core contains a reference design for the MPX8349FA module. For more information pls. email: office@wiese.de or info@microsys.de |
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